Hardware Development Engineer – Chip Timing (f/m/x)

Join a Team That Builds the Future of Computing At IBM’s largest European R&D site in Ehningen, Germany, innovation is a team effort. With 1,300 employees and around 200 engineers in our hardware development team, we’re shaping the future of computing—together. We design the core components behind IBM Z, IBM POWER, and IBM Quantum systems—technologies that power cloud computing, AI, big data, and more. What sets us apart is how we work: across borders, disciplines, and product families. You’ll collaborate with colleagues in the U.S., Israel, and India, using AI, Agile and Design Thinking to drive creativity and continuous learning. If you're passionate about technology and thrive in a collaborative, forward-thinking environment, we’d love to meet you. Your Role: Timing Engineer We’re hiring Development Engineers (f/m/x) to join our Processor Physical Design team starting January 1, 2027. The team is responsible for designing and implementing powerful server processors for IBM Z and IBM POWER server as well as essential chips for IBM Quantum systems. Key Areas of Work As a Timing Engineer, you will be part of a multidisciplinary team driving the delivery of timing-closed, manufacturable chip designs in leading-edge semiconductor technologies. You will work across the full design cycle, taking on a diverse set of responsibilities that are critical to the success of next-generation IBM processors and chips. Perform static timing analysis (STA) to verify processor designs meet frequency and timing requirements Analyze timing violations and identify root causes across multiple design stages Analyze and validate simulation based timing rules Collaborate with logic, circuit, physical design, and methodology teams to resolve timing issues Support synthesis, place-and-route, clock implementation, and design optimization activities Develop scripts and automation to improve timing analysis efficiency and design quality Participate in design reviews and contribute to signoff readiness Learn and apply timing tools and design methodologies Help drive continuous improvements in timing closure methodologies and design flows with the introduction of new AI-based tools and concepts Your Team & Work Environment A modern, agile development environment Flexible working hours and a secure workplace Early responsibility with mentorship support Tailored development for technical, leadership, or project management careers Opportunities to apply IBM Bob and other AI tools in daily engineering work We’re looking for candidates with a strong technical foundation and a collaborative mindset. Ideally, you have: University degree (Bachelor, Master, PhD) in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a related field Solid understanding of digital circuit design Knowledge of analog circuit design is an advantage Experience with circuit simulation tools like SPICE Experience in static timing analysis (STA) is an advantage Knowledge in the domain of clock distribution (e.g. clock trees or grids) and clock circuits (e.g. oscillators or PLLs) is an advantage Experience with CAD tools for the physical design flow (e.g. Cadence, Synopsys) is an advantage Programming experience (preferably Python) Experience with CI/CD tools (e.g. Git, Jenkins) is an advantage Experience with AI-assisted development tools, coding assistants, or workflow automation is an advantage Strong intrinsic motivation and proactive attitude Curiosity and enthusiasm for experimentation, problem-solving, and debugging Strong team player and open minded to work in an international team Strong communication skills in English and German Please submit a complete application package, including: Cover letter Curriculum Vitae (CV) Academic transcripts, including a detailed grade overview Employment references or letters of recommendation (if available) .